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ICS9LRS3187B idt ? programmable timing control hub for intel based systems 1602f?11/04/11 datasheet programmable timing control hub for intel based systems 1 recommended application: features/benefits: ck505 version 1.1 clock, with fully integrated voltage regulators and series resistors ? supports spread spectrum modulation, 0 to -0.5% down spread for cpu and src clocks ? uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning ? available in commercial (0 to +70c) and industrial (-40 to +85c) temperature ranges ? meets pcie gen2 specifications pin configuration output features: ? 2 - cpu differential low power push-pull pairs ? 1 - src differential low power push-pull pair ? 1 - sata differential low power push-pull pair ? 1 - dot differential low power push-pull pair ? 1 - ref, able to drive 3 loads, 14.318mhz ? 1 - 27mhz_ss/non_ss single-ended output pair 32-pin mlf ? cpu outputs cycle-cycle jitter <85ps ? src outputs cycle-cycle jitter <125ps ? +/- 100ppm frequency accuracy on all clocks key specifications: sclk_3.3 sdata_3.3 ref_2l/fslc_3.3** vddref_3.3 x1 x2 gndref clkpwrgd/pd#_3.3 32 31 30 29 28 27 26 25 vdddot96mhz_3.3 1 24 vddcpu_3.3 gnddot96mhz 2 23 cput0_lpr dot96t_lpr 3 22 cpuc0_lpr dot96c_lpr 4 21 gndcpu vdd_27mhz 5 20 cput1_lpr 27mhz_nonss 6 19 cpuc1_lpr 27mhz_ss 7 18 vddcpu_io gnd27mhz 8 17 vddsrc_3.3 9 10111213141516 gndsata satat_lp r satac_lpr gndsrc srct1_lpr srcc1_lpr vddsrc_io *cpu_stop# ** internal pull-down resistor * internal pull-up resistor 9lrs3187
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 2 datasheet pin description pin# pin name type pin description 1 vdddot96mhz_3.3 pwr power pin for the 96mhz output 3.3v. 2 gnddot96mhz pwr ground pin for the 96mhz output 3 dot96t_lpr out true dot96 output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 4 dot96c_lpr out complement dot96 output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 5 vdd_27mhz pwr power pin for the 27mhz output 3.3v. 6 27mhz_nonss out 3.3v single-ended 27mhz non-spread clock. 7 27mhz_ss out 3.3v single-ended 27mhz spread clock. 8 gnd27mhz out ground pin for the 27mhz outputs. 9 gndsata pwr ground pin for the sata outputs. 10 satat_lpr out true clock of differential 0.8v push-pull sata/src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 11 satac_lpr out complementary clock of differential 0.8v push-pull sata/src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 12 gndsrc pwr ground pin for the src outputs 13 srct1_lpr out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 14 srcc1_lpr out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 15 vddsrc_io pwr 1.05v to 3.3v from external power supply 16 *cpu_stop# in stops all cpu clocks, except those set to be free r unning clocks 17 vddsrc_3.3 pwr supply for src clo cks, 3.3v nominal 18 vddcpu_io pwr 1.05v to 3.3v from external power supply 19 cpuc1_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 20 cput1_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 21 gndcpu pwr ground pin for the cpu outputs. 22 cpuc0_lpr out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 23 cput0_lpr out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 24 vddcpu_3.3 pwr supply for cpu clo cks, 3.3v nominal 25 clkpwrgd/pd#_3.3 in notifies ck505 to sample latched inputs, or pwrdwn# mode 26 gndref pwr ground pin for the ref outputs. 27 x2 out crystal output, nominally 14.318mhz 28 x1 in crystal input, nominally 14.318mhz 29 vddref_3.3 pwr power pin for the xtal and ref clo cks, nominal 3.3v 30 ref_2/fslc_3.3** i/o 14.318 mhz reference clock, which can drive 2 loads / 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 31 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant 32 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant.
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 3 datasheet functional block diagram general description the ICS9LRS3187B is a ck505 clock synthesizer. the ICS9LRS3187B provides a single-chip solution for intel based systems. the ICS9LRS3187B is driven with a 14.318mhz crystal. ss pll non-ss pll cpuclk ( 1:0 ) 14.318m xt a l src ( 1 ) 27mhz_ss dot96mhz refclk sata_nonss cpuclk cout_div sata 0 1 src b0b1 27mhz nonss ss pll pll table: power distribution ground vdd_io vdd 3.3v out p u t 2 1dot96 8 5 27m 915 17 sata 12 15 17 src 21 18 24 cpu 26 29 ref
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 4 datasheet table 1: cpu frequency select table fs l c b0b7 cpu mhz src mhz ref mhz dot mhz 0 (default) 133.33 1 100.00 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 14.318 96.00 table 2: pin 6, 7 configuration pin 6 pin 7 spread mhz mhz % 000 27mhz_nonss 27mhz_ss -1.75% 001 27mhz_nonss 27mhz_ss +-0.5% 010 27mhz_nonss 27mhz_ss -0.5% default 011 27mhz_nonss 27mhz_ss -1% 100 27mhz_nonss 27mhz_ss -1.5% 101 27mhz_nonss 27mhz_ss -2% 110 27mhz_nonss 27mhz_ss -0.75% 111 27mhz_nonss 27mhz_ss -1.25% b1b3 b1b2 b1b1 comment table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1.0v
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 5 datasheet 1 1 enable running running running running 0 x enable low/20k low low/20k low 1 0 enable high low high low 1x disable low/20k low low/20k low running running low/20k low cpu power management table pd# cpu_stop# smbus re g . oe cpu1 cpu1# cpu0 cpu0# m1 src and dot96mhz power management table 0 x enable low/20k low low/20k low 1 x enable running running running running 1x disable low/20k low low/20k low low/20k low low/20k low pd# cpu_stop# smbus reg. oe src src# dot dot# m1 singled-ended power management table 1 x enable running running 0 x enable low hi-z 1x disable low low low hi-z ref pd# cpu_stop# smbus re g . oe m1 27m
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 6 datasheet general smbus serial interface information for the ICS9LRS3187B how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit idt (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit idt (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 7 datasheet byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 - fslc cpu fre q . sel. bit r latch 6 - reserved reserved rw - - 0 5 - reserved reserved rw - - 1 4 - iamt_en set via smbus rw ( stick y "1" ) legacy mode iamt enabled 0 3 reserved reserved rw 0 2 - reserved reserved rw 0 1 - sata_sel select source for sata clock rw sata (src2 100mhz_ss) = src_main sata (100mhz non_ss) = sata pll 0 0- pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power - on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 dot96 select and pll3 quick config register, bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 src_pll_ssc_sel select 0.5% down or center ssc rw down s p read center s p read 0 5 reserved reserved rw - - 1 4 reserved reserved rw 0 3 27ss pll cf2 27ss pll quick confi g bit 2 rw 0 2 27ss pll _cf1 27ss pll quick confi g bit 1 rw 1 1 27ss pll cf0 27ss pll quick confi g bit 0 rw 0 0 reserved reserved rw - - 1 byte 2 output enable register bit pin name description type 0 1 default 7 ref_3l_oe output enable for ref0, if disabled output is tri- stated rw output disabled output enabled 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 reserved reserved rw - - 1 3 reserved reserved rw - - 1 2 reserved reserved rw - - 1 1 reserved reserved rw - - 1 0 reserved reserved rw - - 1 byte 3 output enable register bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 reserved reserved rw - - 1 3 reserved reserved rw - - 1 2 reserved reserved rw - - 1 1 reserved reserved rw 1 0 reserved reserved rw - - 1 see table 2: pin 6/7 configuration
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 8 datasheet byte 4 output enable and spread spectrum disable register bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 sata_oe out p ut enable for sata rw out p ut disabled out p ut enabled 1 5 src1_oe out p ut enable for src1 rw out p ut disabled out p ut enabled 1 4 dot96_oe out p ut enable for dot96 rw out p ut disabled out p ut enabled 1 3cpu1_oe out p ut enable for cpu1 rw out p ut disabled out p ut enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 27ss_on enable 27ss's spread modulation rw spread disabled spread enabled 1 0 src_ssc_on enable src's spread modulation rw spread disabled spread enabled 1 byte 5 reserved register bit pin name description type 0 1 default 7 reserved reserved rw - - 1 6 reserved reserved rw - - 1 5 reserved reserved rw - - 1 4 reserved reserved rw - - 1 3 reserved reserved rw - - 1 2 reserved reserved rw - - 1 1 reserved reserved rw - - 1 0 reserved reserved rw - - 1 byte 6 slew rate control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 ref slew slew rate control rw 2 v/ns 1 v/ns 0 4 reserved reserved rw - - 0 3 27mhz slew slew rate control rw 2 v/ns 1 v/ns 0 2 reserved reserved rw -- 0 1 reserved reserved rw - - 0 0 reserved reserved rw - - 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id and output enable register bit pin name description type 0 1 default 7 device_id3 r 1 6 device_id2 r 0 5 device_id1 r 0 4 device_id0 r 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 27mhz_nonss_oe output enable for 27mhz_nonss rw disabled enabled 1 0 27mhz_ss_oe output enable for 27mhz_ss rw disabled enabled 1 table of device identifier codes, used for differentiating between ck505 package options, etc. see device id table revision id vendor specific vendor id ics is 0001, binary
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 9 datasheet byte 9 output control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved r --0 5 reserved reserved rw - - 1 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io output voltage select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 byte 10 output control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 reserved reserved rw - - 0 5 reserved reserved rw - - 0 4 reserved reserved rw - - 0 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu 0 stop enable enables control of cpu 0 with cpu_stop# rw free running stoppable 1 byte 11 reserved register bit pin name description type 0 1 default 7 reserved reserved rw 0 6 reserved reserved rw 0 5 reserved reserved rw 0 4 reserved reserved rw 0 3 reserved reserved rw - - 0 2 cpu1_amt_en m1 mode clk enable rw disable enable 1 1 pci-e_gen2 determines if pci-e gen2 compliant r non-gen2 pci-e gen2 compliant 1 0 reserved reserved rw - - 1 byte 12 byte count register bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 1 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 read back byte count register, max bytes = 32 see table 3: v_io selection (default is 0.8v)
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 10 datasheet absolute maximum ratings - dc parameters, commercial temperature range parameter symbol conditions min typ max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 1 maximum input voltage v ih 3.3v inputs 4.6 v 1,2 minimum input voltage v il any input gnd - 0.5 v 1 storage temperature ts - -65 150 c 1 input esd protection esd prot human body model 2000 v 1,3 1 operation under these conditions is neither implied, nor guaranteed. notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 2 maximum vih is not to exceed vdd 3 human body model electrical characteristics - input/supply/common output dc parameters, commercial temperature range parameter symbol conditions min typ max units notes ambient operating temp tambient - 0 70 c supply voltage vddxxx supply voltage 3.135 3.465 v supply voltage vddxxx_io low-voltage differential i/o supply 0.9975 3.465 v 5 input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v 3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 3 low threshold input- fsc = '1' voltage v ih_fsc 3.3 v +/-5% 0.7 3.3 v 4 low threshold input-low voltage v il_fsc 3.3 v +/-5% v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3. 3 full active, c l = full load; idd 3.3v 85 110 ma i ddopi o full active, c l = full load; idd io 18 25 ma 5 i ddiamt3. 3 m1 mode, 3.3v rail 48 60 ma i ddiamti o m1 mode, io rail 6 10 ma 5 i ddpd3. 3 power down mode, 3.3v rail 6 5 ma i ddpdi o power down mode, io rail 0 0.1 ma 5 input frequency f i v dd = 3.3 v 14.3182 15 mhz pin inductance l pin 7nh c in logic inputs 1.5 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.0 1.8 ms tfall_se t fall 10 ns 1 trise_se t rise 10 ns 1 smbus voltage v dd 2.7 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 5 ma sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 32.54 33 khz 1 signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 4 frequency select pins which have tri-level input 5 if present, not all parts have this feature. powerdown current input capacitance fall/rise time of all 3.3v control inputs from 20-80% 3 3.3v referenced inputs are: sclk, sdata, and ckpwrgd notes: ( unless otherwise noted, g uaranteed b y desi g n and characterization, not 100% tested in p roduction ) . operating supply current iamt mode current
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 11 datasheet ac electrical characteristics - low power differential outputs, commercial temperature range parameter symbol conditions min typ max units notes rising edge slew rate tslr averaging on 2.5 3.7 4 v/ns 2, 3 falling edge slew rate tflr averaging on 2.5 3.7 4 v/ns 2, 3 slew rate variation tslvar averaging on 3.6 20 % 1, 6 differential voltage swing vswing averaging off 300 mv 2 crossing point voltage vxabs averaging off 300 446 550 mv 1,4,5 crossing point variation vxabsvar averaging off 70 140 mv 1,4,9 maximum output voltage vhigh averaging off 1150 mv 1,7 minimum output voltage vlow averaging off -300 mv 1,8 duty cycle dcyc averaging on 45 49.8 55 % 2 cpu skew cpuskew averaging on 35 100 ps src skew t skewsrc averaging on, src to sata skew when byte0, bit 1 = 0 259 350 ps 1 measurement taken for single ended waveform on a component test board (not in system) 2 measurement taken from differential waveform on a component test board. (not in system) 3 slew rate emastured through v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#, measured on a component test board (not in system) 5 only applies to the differential rising edge (clock rising, clock# falling) 7 the max voltage including overshoot. 8 the min voltage including undershoot. 9 the total variation of all vcross measurements in any particular system. note this is a subset of v_cross min/mas (v_cross ab solute) allowed. the intent is to limit vcross induced modulation by setting c_cross_delta to be smaller than v_cross absolute 6 matchin g applies to risin g ed g e rate for clock and fallin g ed g e rate for clock#. it is measured usin g a +/-75mv window centered on the avera g e cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). c l = 2pf, rs = 0 ohms. clock jitter specs - low power differential outputs, commercial temperature range parameter symbol conditions min typ max units notes cpu jitter - cycle to cycle cpujc2c differential measurement 50 85 ps 1 src/sata jitter - cycle to cycle srcjc2c differential measurement 50 125 ps 1,2 dot jitter - cycle to cycle dotjc2c differential measurement 50 250 ps 1 t jphasepll pcie gen 1 35 86 ps (p- p) 1,2,3 t jphaselo pcie gen 2 10khz < f < 1.5mhz 1.8 3 ps (rms) 1,2,3 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.3 3.1 ps (rms) 1,2,3 notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). c l = 2pf, rs = 0 ohms. 1 jitter specs are specified as measured on a clock characterization board. system designers need to take special care not to us e these numbers, as the in-system performance will be somewhat degraded. the receiver emts (chispet or cpu) will have the receiver jitter specs as measured in a real system. 2 phase jitter requirement: the designated gen2 outputs will meet the reference clock jitter requirements from the pci express g en2 base spec. the test is performed on a component test board under quiet conditions with all outputs on. src phase jitter 3 see http://www.pcisig.com for complete specs
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 12 datasheet electrical characteristics - ref-14.318mhz, commercial temperature range parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 2, 4 clock period tperiod 14.318mhz output nominal 69.82033 69.84129 69.86224 ns 2, 3 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 2 clk high time thigh 29.97543 38.46654 v clk low time tlow 29.57543 38.26654 v output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma rising/falling edge slew rate t slew measured between 0.8 to 2.0 v 1 1.7 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 53 55 % 2 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 115 1000 ps 2 1 edge rate in system is measured from 0.8v to 2.0v. 2 duty cycle, peroid and jitter are measured with respect to 1.5v 3 the average period over any 1us period of time notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 4 using frequency counter with the measurment interval equal or greater that 0.15s, target frequency is 14.318180 mhz electrical characteristics - 27mhz_spread / 27mhz_nonspread, commercial temperature range parameter symbol conditions min typ max units notes -50 50 1,2 -15 15 1,2,3 clock period t period 27.000mhz output nominal 37.0365 37.0376 output high current i oh voh @min = 1.0 v, voh@max = 3.135 v -29 -23 ma 1 output low current i ol vol @min = 1.95 v, vol @max = 0.4 v 29 27 ma 1 rising/falling edge slew rate t slewr/f rising/falling edge rate 1 2 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 50.4 55 % 1 t lt j long term (10us) 485 800 ps t jp k- p k v t = 1.5 v -100 100 ps t j c y c-c y c v t = 1.5 v 57 120 ps v t = 1.5 v ss% <= 1.5% pk to pk 82 200 ps 4 v t = 1.5 v, ss% > 1.5% pk to pk 134 200 ps 4 1 edge rate in system is measured from 0.8v to 2.0v at default slew rate control setting. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref out is at 14.31818mhz 3 at nominal temperature and voltage. 4 long term and peak to peak jitter do not apply to the 27mhz spreading output. the spread modulation directly impacts these val ues. notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). jitter, 27mhz_nonspread output jitter, 27mhz_spread output t jcyc-cyc long accuracy ppm see tperiod min-max values ppm
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 13 datasheet absolute maximum ratings - dc parameters, industrial temperature range parameter symbol conditions min typ max units notes maximum supply voltage vdd xxx supply voltage 4.6 v 1 maximum supply voltage vdd xxx_io low-voltage differential i/o supply 3.8 v 1 maximum input voltage v ih 3.3v tolerant inputs 4.6 v 1,2 minimum input voltage v il any input gnd - 0.5 v 1 storage temperature ts - -65 150 c 1 input esd protection esd prot human body model 2000 v 1,3 1 o p eration under these conditions is neither im p lied, nor g uaranteed. notes: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 2 maximum vih is not to exceed vdd 3 human bod y model electrical characteristics - input/supply/common output dc parameters, industrial temperature range parameter symbol conditions min typ max units notes ambient operating temp t ambind industrial range -40 85 c supply voltage, core vdd xxx supply voltage 3.135 3.3 3.465 v supply voltage, i/o vdd xxx_io low-voltage differential i/o supply 0.9975 1.05 3.465 v 5 input high voltage v ihse single-ended 3.3v inputs 2 2.4 v dd + 0.3 v 3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.4 0.8 v 3 low threshold input - high voltage v ih_fsc 3.3 v +/-5%, voltage for which fsc = '1' 0.7 3.3 v 4 low threshold input - low voltage v il_fs c 3.3 v +/-5% v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i i nres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3. 3 full active, c l = full load; idd 3.3v 92 110 ma i ddopi o full active, c l = full load; idd io 18 25 ma 5 i ddiamt3. 3 m1 mode, 3.3v rail 48 65 ma i ddiamti o m1 mode, io rail 6 15 ma 5 i ddpd3. 3 power down mode, 3.3v rail 3.2 8 ma i ddpdi o power down mode, io rail 0 0.05 ma 5 input frequency f i v d d = 3.3 v 14.318 15 mhz pin inductance l p in 57nh c in logic inputs 1.5 4 5 pf c out output pin capacitance 5 6 pf c inx x1 & x2 pins 4 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tfall_se t fall 10 ns 1 trise_se t ri se 10 ns 1 smbus voltage v d d 2.7 3.3 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 5 ma sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to ( min vih + 0.15 ) 1000 ns sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 32.54 33 khz 1 si g nal is required to be monotonic in this re g ion. 2 input leaka g e current does not include inputs with pull-up or pull-down resistors 4 frequency select pins which have tri-level input 5 if p resent, not all p arts have this feature. powerdown current input capacitance fall/rise time of all 3.3v control inputs from 20-80% operating supply current iamt mode current notes: ( unless otherwise noted, g uaranteed b y desi g n and characterization, not 100% tested in p roduction ) . 3 3.3v referenced in p uts are: sclk, sdata, and ckpwrgd
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 14 datasheet ac electrical characteristics - low power differential outputs, industrial temperature range parameter symbol conditions min typ max units notes rising edge slew rate t slr averaging on 2.5 3.7 4.2 v/ns 2, 3 falling edge slew rate t fl r averaging on 2.5 3.7 4.2 v/ns 2, 3 slew rate variation t slvar averaging on 12.2 20 % 1, 6 differential voltage swing v swing averaging off 300 mv 2 crossing point voltage vx abs averaging off 300 447 550 mv 1,4,5 crossing point variation vx absva r averaging off 19 140 mv 1,4,9 maximum output voltage v hi gh averaging off 941 1150 mv 1,7 minimum output voltage v low averaging off -300 -43 mv 1,8 duty cycle dcyc averaging on 45 49.8 55 % 2 cpu skew t skewcpu averaging on 35 100 ps src skew t skewsrc averaging on, src to sata skew when byte0, bit 1 = 0 288 350 ps 1 measurement taken for single ended waveform on a component test board (not in system) 2 measurement taken from differential waveform on a component test board. (not in system) 3 slew rate measured through mimimum v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#, measured on a component test board (not in system) notes: (unless otherwise noted, g uaranteed by desi g n and characterization, not 100% tested in production). c l = 2pf, rs = 0 ohms. 5 only applies to the differential rising edge (clock rising, clock# falling) 6 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window center ed on the average cross point where clock risin g meets clock# fallin g . the median cross p oint is used to calculate the volta g e 7 the max voltage including overshoot. 8 the min voltage including undershoot. 9 the total variation of all vcross measurements in any particular system. note this is a subset of v_cross min/max (v_cross ab solute) allowed. the intent is to limit vcross induced modulation by setting c_cross_delta to be smaller than v_cross absolute clock jitter specifications - low power differential outputs, industrial temperature range parameter symbol conditions min typ max units notes cpu jitter - cycle to cycle cpuj c2 c differential measurement 55 85 ps 1 src jitter - cycle to cycle srcj c2 c differential measurement 55 125 ps 1 sata jitter - cycle to cycle sataj c2c differential measurement 55 125 ps 1 dot jitter - cycle to cycle dotj c2 c differential measurement 55 250 ps 1 t jp hasepll pcie gen 1 45 86 ps (p-p) 1,2,3 t jphaselo pcie gen 2 10khz < f < 1.5mhz 23 ps (rms) 1,2,3 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.6 3.1 ps (rms) 1,2,3 1 jitter specs are specified as measured on a clock characterization board. system designers need to take special care not to us e these numbers, as the in-system performance will be somewhat degraded. the receiver emts (chispet or cpu) will have the receiver jitter specs as measured in a real system. 2 phase jitter requirement: the designated gen2 outputs will meet the reference clock jitter requirements from the pci express g en2 base spec. the test is performed on a component test board under quiet conditions with all outputs on. src phase jitter 3 see http://www.pcisig.com for complete specs notes: (unless otherwise noted, g uaranteed by desi g n and characterization, not 100% tested in production). c l = 2pf, rs = 0 ohms.
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 15 datasheet electrical characteristics - ref-14.318mhz, industrial temperature range parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 2, 4 clock period tperiod 14.318mhz output nominal 69.82033 69.84129 69.86224 ns 2, 3 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 2 clk high time thigh 29.97543 38.46654 v clk low time tlow 29.57543 38.26654 v output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -33 -33 ma output low current iol vol @min = 1.95 v, vol @max = 0.4 v 30 38 ma rising/falling edge slew rate t slew measured between 0.8 to 2.0 v 1 1.8 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 52.8 55 % 2 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 122 500 ps 2 1 edge rate in system is measured from 0.8v to 2.0v at default slew rate control setting. 2 duty cycle, peroid and jitter are measured with respect to 1.5v 3 the average period over any 1us period of time notes: ( unless otherwise noted, g uaranteed b y desi g n and characterization, not 100% tested in p roduction ) . 4 using frequency counter with the measurment interval equal or greater that 0.15s, target frequency is 14.318180 mhz electrical characteristics - 27mhz_spread / 27mhz_nonspread, industrial temperature range parameter symbol conditions min typ max units notes -50 50 1,2 -15 15 1,2,3 clock period t period 27.000m outputs, 27m ss with ss off 37.0365 37.0376 output high current i oh voh @min = 1.0 v, voh@max = 3.135 v -29 -23 ma output low current i ol vol @min = 1.95 v, vol @max = 0.4 v 29 27 ma rising/falling edge slew rate t slew measured between 0.8 to 2.0 v 1 2 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 50.4 55 % t lt j long term (10us) 485 800 ps t jp k- p k v t = 1.5 v -100 100 ps t j c y c-c y c v t = 1.5 v 57 120 ps v t = 1.5 v ss% <= 1.5% pk to pk 108 200 ps 4 v t = 1.5 v, ss% > 1.5% pk to pk 140 200 ps 4 1 edge rate in system is measured from 0.8v to 2.0v at default slew rate control setting. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref out is at 14.31818mhz 3 at nominal temperature and voltage. 4 long term and peak to peak jitter do not apply to the 27mhz spreading output. the spread modulation directly impacts these val ues. notes: (unless otherwise noted, g uaranteed by desi g n and characterization, not 100% tested in production). jitter, 27mhz_nonspread output long accuracy ppm see tperiod min-max values ppm jitter, 27mhz_spread output t jcyc-cyc
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 16 datasheet suggested suggested termination resistors for various driving conditions are as follows for transmission lines with zo = 50 ohms: driving 1 load, rs = 39 ohms driving 2 loads, rs = 22 ohms driving 1 load, rs = 39 ohms driving 2 loads, rs = 22 ohms 27m ss and non-ss outputs ref output test load single ended outputs cl=5pf rs zo rs zo rs zo cl=5pf cl=5pf
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 17 datasheet clock periods differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock - c-c jitter -ssc -ppm error 0ppm + pp m error +ssc + c-c jitter absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e absolute period minimum minimum minimum nominal maximum maximum maximum src 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2 cpu 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2 cpu 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2 cpu 200 4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2 cpu 266 3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2 cpu 333 2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2 cpu 400 2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2 clock periods differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock - c-c jitter -ssc -ppm error 0ppm + pp m error +ssc + c-c jitter absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e absolute period minimum minimum minimum nominal maximum maximum maximum src 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2 cpu 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2 cpu 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2 cpu 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2 cpu 200 4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2 cpu 266 3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2 cpu 333 2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2 cpu 400 2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2 dot 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2 notes: 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz signal name signal name measurement window units notes symbol definition measurement window units notes symbol definition
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 18 datasheet test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z) hw s w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt ? programmable timing control hub for intel based systems 1602f?11/04/11 ICS9LRS3187B programmable timing control hub for intel based systems 19 datasheet a0.81.0 n 32 a1 0 0.05 n d 8 a3 n e 8 b 0.18 0.3 d x e basic 5.00 x 5.00 e d2 min. / max. 3.0/ 3.3 e2 min. / max. 3.0/ 3.3 l min. / max. 0.30 / 0.50 0.20 reference 0.50 basic ics 32l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. symbol dimensions marking diagrams ordering information part / order number shipping package package temperature 9lrs3187bklf tubes 32-pin mlf 0 to +70 c 9lrs3187bklft tape and reel 32-pin mlf 0 to +70 c 9lrs3187bkilf tubes 32-pin mlf -40 to +85 c 9lrs3187bkilft tape and reel 32-pin mlf -40 to +85 c ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (will not correlate to the datasheet revision). ics s3187bil yyww coo lot ics rs3187bl yyww coo lot
ICS9LRS3187B programmable timing control hub for intel based systems datasheet innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa 20 revision history a 04/13/10 rdw released to final b 04/15/10 rdw revised commercial and industrial electrical tables for consistency c 06/02/10 lpl added features bullet: meets pcie gen2 specifications 1 d 10/01/10 lpl updated pins 1/2 descriptions 2 e 04/29/11 rdw updated marking diagrams 19 f 11/04/11 dc updated cpu/src specs under key specifications 1

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